The present invention relates to a semiconductor integrated device having a complementary metal oxide semiconductor (CMOS) structure. More particularly, this invention relates to a semiconductor integrated device capable of reducing power dissipation, and a method of designing such a semiconductor integrated device.
Due to advance of frontier techniques, fabrication of fast, highly integrated, large scale integrated circuits (xe2x80x9cICsxe2x80x9d) has become possible in recent years. Therefore, construction of a fast, large capacity system has become possible. In such a system, however, an increase in power dissipation poses a problem. It has become very important to reduce the power dissipation of ICs used in devices in the system. By the way, the power dissipation of each IC is determined by charge and discharge currents of transistors that flow in order to activate the IC, through currents of transistors flowing at the time of IC operation, leakage currents of transistors flowing at the time of standstill of the IC, and so on.
As a conventional semiconductor integrated device in which a major part of power dissipation is occupied by the above described charge and discharge currents, a semiconductor integrated device having, for example, a CMOS structure (hereafter referred to as CMOS circuit) will now be described.
FIG. 17 is a diagram showing the current path of the conventional CMOS circuit. Reference number 101 denotes a PMOS transistor, and reference number 102 denotes a NMOS transistor. Moreover, reference number 104 denotes a power supply, and reference number 105 denotes ground connection (xe2x80x9cGNDxe2x80x9d). Thus, an inverter circuit is formed. Reference number 103 denotes a load capacitor caused by wiring connected to an output of the inverter circuit and a circuit of a subsequent stage.
Following currents flow through this inverter circuit. That is, a through current 111, a charge current 112, and a discharge current 113. In switchover of xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d of the PMOS transistor 101 and the NMOS transistor 102, the through current 111 flows from the power supply 104 to the GND 20 through the PMOS transistor 101 and the NMOS transistor 102, when both the PMOS transistor 101 and the NMOS transistor 102 temporarily turn xe2x80x9cON.xe2x80x9d When the PMOS transistor 101 is xe2x80x9cON,xe2x80x9d the charge current 112 flows from the power supply 104 into the load capacitance 103 through the PMOS transistor 101. When the NMOS transistor 102 is xe2x80x9cON,xe2x80x9d the discharge current 113 flows from the load capacitor 103 into the GND 105 through the NMOS transistor 102.
By the way, power dissipation P caused by the charge current 112 and the discharge current 113 can be represented by equation (1)
P=(xc2xd) CV2xe2x80x83xe2x80x83(1) 
FIG. 18 is a diagram showing an example of a conventional semiconductor integrated device. FIG. 19 is a time chart showing operation of the conventional semiconductor integrated device. In FIG. 18, reference numeral 100 denotes an IC chip made of a CMOS element. Reference numerals 2, 3, 4, 10 and 11 denote independent internal block circuits in the IC chip 100. Reference numeral 5 denotes an inverter circuit functioning as a driver of a clock signal clk. Reference numeral 6 denotes a plurality of flip-flop circuits. Reference numeral 7 denotes an internal block circuit included in the internal block circuit 4. Reference numerals 8 and 13 denote composite gate circuits. Reference numerals 9 and 12 denote driver circuits. Reference symbols a, b, c, d, e, clk, 5o, 6a, 6b, 6c, 6d, 6e, 7a, 7b, 7c, 7d, 7e, 8o and 9o denote signals.
First of all, in the IC chip 100, for example, signals such as an output signal a of the internal block circuit 2, an input signal b input from the outside, a signal c generated within the internal block circuit 4, a signal d generated outside the internal block circuit 4, an output signal e of the internal block circuit 3 are individually output to the flip-flop circuits 6. The flip-flop circuits 6 latch the received signal at a falling edge of a clock signal 5o received via the inverter circuit 5.
The internal block circuit 7 receives the signals 6a to 6e output from the flip-flop circuits 6, generates and outputs signals 7a to 7e. 
Upon receiving output signals 7a to 7e of the internal block circuit 7, the composite gate circuit 8 outputs a signal 8o assembled therein. The driver circuit 9 outputs a signal 9o having predetermined drive capability. Thereafter, the output signal 9o is transmitted to a plurality of circuits located inside and outside the internal block circuit 4.
Operation of the IC chip 100 will now be explained in detail with reference to FIG. 19. Reference symbols A, A1, A2, A3, B, B1, B2, C1, C2, D, D1, D2, D3, E, E1, E2 and E3 denote signal data of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Reference characters tda, tdb, tdc, tdd and tde denote delay time of data. Reference symbols (ixe2x88x921), i, and (i+1) denote periods. Reference symbols 9(ixe2x88x921), 9i, and 9(i+1) denote output values of the driver circuit 9 in the period (ixe2x88x921), period i, and period (i+1), respectively.
First, data of signals a to e received by the internal block circuit 4 are latched by a falling edge of the clock signal 5o in the (ixe2x88x921) period. Since at this time the signals a to e are latched by the same clock signal 5o, the output signals 6a to 6e simultaneously change to xe2x80x9cA1xe2x80x9d, xe2x80x9cBxe2x80x9d, xe2x80x9cC1xe2x80x9d, xe2x80x9cD1xe2x80x9d and xe2x80x9cExe2x80x9d.
Data of the flip-flop circuits 6 are passed through individual paths in the internal block circuit 7 and output. When output from the internal block circuit 7, therefore, the delay times tda, tdb, tdc, tdd and tde of respective paths are added. In other words, the output signals 7a to 7e of the internal block circuit 7 changes to data xe2x80x9cA1xe2x80x9d, xe2x80x9cBxe2x80x9d, xe2x80x9cC1xe2x80x9d, xe2x80x9cD1xe2x80x9d and xe2x80x9cExe2x80x9d at respective time points.
Subsequently, data output from the internal block circuit 7 are assembled in the composite gate circuit 8 to produce the signal 8o. Furthermore, the signal 8o is converted in the driver circuit 9 to the signal 9o having predetermined drive capability. Thereafter, the signal 9o is transmitted to a plurality of circuits provided inside and outside the internal block circuit 4.
When different delay times are added to a plurality of synchronized signals because of difference in path as in the above described conventional semiconductor circuit apparatus, however, there is a possibility that, for example, the output signal 8o of the composite gate circuit 8 of a subsequent stage will operate irregularly depending upon changes of the input signals until changes of all input signals are completed. Furthermore, an irregular change of the output signal 8o is also propagated/reflected to the output signal 9o of the driver circuit 9 following the composite gate circuit 8, and thereafter the change is propagated to all subsequent circuits.
In this way, in the conventional semiconductor integrated device, the above described irregularly changing signal is propagated to all subsequent circuits. Although the signal change is unnecessary in the circuit operation, charge and discharge currents flow as a result of this signal change, resulting in a problem.
Furthermore, since the unnecessary signal change is propagated to all subsequent circuits as described above, the charge and discharge currents disadvantageously increase as the semiconductor integrated device as a whole becomes large in scale and high in performance.
It is an object of this invention to provide a semiconductor integrated device capable of reducing the charge and discharge currents which are unnecessary for circuit operation, and reducing the power dissipation of the apparatus as a whole.
The semiconductor integrated device according to this invention comprises a control circuit disposed to cope with time difference caused in changes of a plurality of signals by difference in routes. This control circuit outputs a received signal in a definite data interval when changes of all signals have been completed, and outputs a fixed signal irrespective of a signal level of a received signal in an indefinite data interval when changes of all signals have not been completed. The control circuit thus prevents irregular signal changes caused by the time difference before definition of data from being prevented to subsequent circuits.
The method of designing a semiconductor integrated device according to this invention comprises the steps of setting conditions of disposition locations of a control circuit beforehand, searching circuit components and signal operations satisfying the conditions at time of work on CAD, and disposing the control circuit, in response to existence of circuit components and signal operations satisfying the conditions.